Operational Amplifiers Calculator

The summing node is at virtual ground: the op amp does whatever is necessary to keep it there, so the input impedance of the inverting amplifier is exactly R_in, not a high value. This is the first cost of the configuration: if the source has its own output impedance, that impedance becomes part of the gain calculation.

The parameter to watch is noise gain. An inverting amplifier with a gain of −1 has N_G = 2, so it has half the bandwidth: with a TL072 that means 1.5 MHz, not 3 MHz. Noise gain is also what multiplies the input offset voltage, as shown in the last row.

The compensation resistor at the non-inverting input is R_in∥R_f and makes the bias-current voltage drops at the two inputs equal, so the effect of I_b is canceled and only the effect of I_os, which is typically about ten times smaller, remains. With a JFET input it is unnecessary: I_b is already in the picoampere range.

Here noise gain equals signal gain, so bandwidth and errors scale directly with the gain you request. In return, the input impedance is that of the op amp itself, effectively extremely high: this is the configuration to use when the source must not be loaded.

The gain cannot fall below one: R_f = 0 gives an exact voltage follower. It provides no voltage gain, and that is precisely why it is useful: it converts a high source impedance into a low output impedance, provides the full op-amp bandwidth, and has a DC error equal only to V_os.

Be careful when using a voltage follower with an op amp that is not unity-gain compensated: some devices, known as decompensated, are stable only above a specified minimum gain and can oscillate at unity gain.

The summing amplifier is an inverting amplifier with several resistors converging on the same summing node. Because that node is at virtual ground, the inputs do not interact with one another: each input is weighted by R_f/R_i , and that is why the circuit works as a mixer.

What is surprising is the bandwidth. Noise gain is not the largest individual weight, but 1+R_f/(R1∥R2∥R3): three 100 kΩ inputs with R_f of 100 kΩ give a gain magnitude of 1 for each input and a noise gain of 4. The individual signal gain is unity, yet the bandwidth is reduced to one quarter and the offset error is multiplied by four. Adding inputs has a cost even when each input gain remains one.

On paper this circuit subtracts two voltages and amplifies their difference. In practice, its subtraction is only as good as the matching of the four resistors. The relation \(\mathrm{CMRR}\simeq\frac{1+R_2/R_1}{4t}\) reveals an unpleasant fact: with 1% resistors you are around 48 dB, so a 5 V common-mode voltage leaves about twenty millivolts of output error, even though the op amp itself specifies 86 dB.

The “required tolerance” field performs the inverse calculation: enter the CMRR you want and it tells you what resistor tolerance is required. For 80 dB at a gain of 10, about 0.03% matching is needed. That is not normally obtained with four unrelated discrete resistors; a monolithic resistor network is the appropriate solution because the elements are fabricated together and track one another with temperature.

Also note that the input impedance is different at the two terminals and depends on the source conditions. This is the other structural limitation of this topology and the reason the next card exists.

Three op amps: two non-inverting input stages with gain, followed by the differential amplifier from Card 4. This solves both limitations described above. The input impedance becomes extremely high and equal at both inputs because the signals are applied directly to the non-inverting terminals.

More importantly, the CMRR improves by the gain of the first stage: that stage amplifies the differential signal by \(1+2R_1/R_g\) while the common-mode gain remains exactly one. Every decibel of first-stage gain therefore adds one decibel of CMRR. With a first-stage gain of 50, the 1% differential stage that provided about 48 dB on its own now reaches roughly 82 dB.

Gain is adjusted with a single resistor, R_g, which does not affect the CMRR resistor matching: it can therefore be adjusted independently. The four resistors in the second stage, however, must remain closely matched, and that is where precision components matter.

An ideal integrator has infinite DC gain, which means that the op amp’s offset voltage—even just a few millivolts—is integrated without limit until the output reaches a rail. On the bench this can happen within seconds. The R_f in parallel with the capacitor closes the DC feedback path and limits the gain to R_f/R: below the corresponding frequency the circuit stops acting as an integrator and becomes an ordinary inverting amplifier, a tradeoff that is usually well worth making.

The differentiator has the complementary problem: its gain increases with frequency, so it amplifies high-frequency noise and, worse, the pole formed in combination with the op amp’s finite bandwidth can make the circuit unstable. The R_s in series with the capacitor limits the high-frequency gain and restores a safer phase margin.

Rule of thumb: choose R_s so that the limiting frequency is about one decade above the useful operating band, while still remaining below the region where the op amp no longer has sufficient loop gain.

The −3 dB bandwidth is a small-signal limit: it applies as long as the output amplitude is low enough not to demand more rate of change than the op amp can provide. Slew rate is a large-signal limit, and the two constraints are fundamentally different.

The calculation is straightforward: a sine wave with peak amplitude V_p at frequency f has a maximum slope of 2πfV_p, and if that slope exceeds the slew rate the output becomes triangular. A 741 has roughly 1 MHz of small-signal bandwidth and about 0.5 V/µs of slew rate: at a 10 V peak amplitude the slew-rate limit is about 8 kHz. This is not a contradiction in the datasheet; it is why slew rate and small-signal bandwidth must be considered separately.

The last line is the one that is often forgotten: output current. A general-purpose op amp may provide only about 20–25 mA, so 10 V across a 200 Ω load is not achievable regardless of bandwidth.

At DC, an op amp does not produce exactly zero output when its input differential voltage is zero, and two main error sources are responsible. The input offset voltage is multiplied by the noise gain, just like an input-referred signal: with N_G = 101 and V_os = 3 mV, the output error is about 300 mV, already around two percent of a 15 V supply magnitude.

Bias current, on the other hand, flows through the resistors and creates voltage drops. This is why high-DC-gain amplifiers using bipolar-input op amps are generally not built with unnecessarily large feedback resistances. The message below the card indicates which error source dominates, which is the key information needed to decide whether to change the topology or the op amp.

With the compensation resistor in the proper location, the error caused by I_b is reduced to the contribution from I_os, typically much smaller. With a JFET or CMOS input, the bias-current problem is usually negligible because I_b is in the picoampere range; at that point V_os, whose value is often worse in those same device families.

The preset values are typical datasheet values, not guaranteed limits: V_os and I_b in particular can vary significantly from device to device and with temperature, and GBW can depend on supply conditions. For a design that must meet its specifications under all conditions, use guaranteed limits rather than typical values.

The CMRR table applies to the four-resistor differential amplifier in Card 4, assuming all four resistors have the same tolerance and worst-case mismatch. It is an upper bound: it indicates the maximum that can be achieved, not the value you are guaranteed to obtain.